Memory Bandwidth Explained
Author: Peter Rundberg.
Posted : 2001-03-07 00:00:00.0
Category : Hardware
Introduction
The age old problem of the widening gap between microprocessor performance and memory performance, sometimes called the "Memory Wall", is getting much attention these days. To combat this problem, advanced memory hierarchies with multilevel caches are present in all modern microprocessors.
New memory technologies like DRDRAM (Rambus) and DDR-SDRAM are also becoming common. These new memory technologies have in common that they provide increased peak memory bandwidth by enhancing the bus between the memory and the microprocessor. Both feature DDR signaling, the possibility of transferring two times per bus cycle, to increase performance. DRDRAM (PC800) use a 16 bit (2 Byte) wide bus running at 400MHz. With DDR signaling this equals 800MHz transfers, giving a peak bandwidth of 1.6GB/s. DDR-SDRAM (PC2100) use a 64 bit bus running at 133MHz. This gives us 266MHz transfers and a 2.1GB/s peak bandwidth.
Notice however that there is a difference between peak bus bandwidth and effective memory bandwidth. Where the peak bus bandwidth is just the product of the bus width and the bus frequency, the effective memory bandwidth includes addressing, and other things that is needed to perform a memory read or write. The bold figures of DDR-SDRAM and DRDRAM does not indicate the how these new memory technologies perform in real life though.
In this article we will look into the cause of the failed promises of these technologies by focusing on the most importand part of memory performance, latency. What neither of these two new memory technologies give us is reduced memory latency, that is the time it takes to look something up in memory. This is because they are both based on DRAM. The latency is not so much an issue of the memory interface as it is the memory cell itself, and since both these two new memories use DRAM, the latency is not improved. As we will see in the following sections, latency is more important than peak bus bandwidth when it comes to providing effective memory bandwidth.